1. Field of the Invention
The present invention relates generally to the design of semiconductor memories and, more particularly, to memories (e.g., static random access memories, or SRAMs) having load devices for enhancing read time.
2. State of the Art
Semiconductor memories, such as SRAMs, typically include an orthogonal array of memory cells arranged in columns and rows for storing data as binary ones and zeros. Data can be written into or read from an addressed memory cell via write and read enable signals, respectively.
Typically, a particular memory cell is addressed by a word select line which includes a column address and a row address. A memory cell located at the intersection of the selected column and row can thus be identified such that binary data may be written into the cell or read out of the cell via bit lines during a write or read operation, respectively.
Two bit lines are associated with each column of an SRAM. Both bit lines are maintained at a given logic level (e.g., logic level high) when data is neither being written into or read from the column of cells.
One of the bit lines is used to represent a logic low condition of an addressed cell in the column, and the other bit line is used to represent a logic high condition of the addressed cell. When a given cell is addressed and enabled during a read operation, the bit line associated with a currently stored logic condition of the cell is pulled low. When the cell is addressed and enabled during a write operation, one of the two bit lines is externally pulled low (i.e., close to ground) to write a logic high or low into the cell.
For example, during a read operation the condition of a memory cell (e.g., logic level high or low) will cause one or the other of the bit lines to drop in voltage level relative to the other bit line. If a stored logic level low causes the first bit line to drop in voltage relative to the second bit line, a stored logic level high would cause the second bit line to drop in voltage relative to the first bit line. During a write operation, an external device (e.g., transistor and/or resistor) is used to pull one of the bit lines low to write a zero or one into the cell.
The speed with which data can be written into or read from a memory cell depends in part on how rapidly the logic levels on the bit lines can change. If a bit line has a low logic level after reading data from a first memory cell, the bit line may transition to a high logic level on reading data from the next sequential memory cell in the column. Significant time is required for the bit line to accommodate this transition in logic levels, thereby limiting the SRAM's operating speed.
It is for this reason that each bit line in a typical SRAM includes a load device with the voltage supply. In known SRAMs, an n-channel or p-channel FET is commonly used as the load device. Gates of the load devices are typically connected to a voltage level representing a logic high level for n-channel load devices or to a logic low level for p-channel load devices.
During a read operation, the load device prevents the bit line voltage with which it is associated from changing significantly. The logic condition of the memory cell is then determined by amplifying the difference between voltage levels on the two bit lines. Accordingly, the time required for recharging the bit lines before reading a subsequent memory cell is decreased such that operating speed of the SRAM is increased.
Although the use of load devices enhances operating speed, it poses several significant drawbacks. Key among these are the operating power requirements associated with the use of load devices. Because load devices prevent the bit lines from traversing the full range of voltage levels associated with logic level low and high conditions during read operations, writing into the cells is rendered more difficult. The added impedance of a load device increases the power requirements necessary to effect writing of logic level lows and highs into the memory cells. The continuously operative load device makes it difficult to pull a bit line low enough to ground to effectively write information into the cell.
Accordingly, larger devices (e.g., transistors more powerful than the load devices) are typically provided to pull the appropriate bit line close to ground during a write operation. Such an arrangement results in substantial current dissipation from the load device. This current becomes significantly higher when the number of cells concurrently written into is increased.
More recent efforts have therefore focused on disabling the load devices during a write operation. For example, known memory devices use an inverted write enable signal to gate the load device or devices. The gates of transistors used as the load devices in each column are tied to the write enable signal through an invertor. If an active high write enable signal initiates a write operation, the inverted write enable deactivates the load devices.
Although the use of an inverted write enable signal to deactivate the load devices avoids significant current dissipation during the write operation, this approach also suffers significant drawbacks. For example, the inverted write enable signal must be routed throughout the entire memory array (i.e., to every bit line) to disable all load devices. This increases the complexity of the memory array architecture as well as the capacitance and power requirements of the write enable signal. Further, the large number of conductive paths associated with the write enable signal produces power surges in these paths each time a write enable is activated or deactivated. These power surges can detrimentally affect overall circuit operation (e.g., disturb the power supply line of the memory).
Accordingly, it would be desirable to provide a memory array architecture which avoids the significant power requirements associated with the use of bit line load devices without suffering the aforementioned drawbacks.